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PRELIMINARY CM3205 DDR VDDQ and Termination Voltage Regulator
Features
* * * * * * * * * * * * * * * 5A continuous current from VDDQ 1.8V to 2.6V adjustable VDDQ output voltage 600-mV typical VDDQ dropout voltage at 5A VTT tracking at 50% of VDDQ Source and sink up to 2A VTT current Excellent load and line regulation, low noise Fast transient response Meets JEDEC DDR-I SDRAM power spec. Linear regulator design requires no inductors and has low external component count Integrated power MOSFETs Dual purpose ADJ/Shutdown pin Built-in over-current limit with short-circuit foldback and thermal shutdown for VDDQ and VTT 5mA quiescent current TO252 andTO263 packages for high performance thermal dissipation and easy PC board layout Optional RoHS Compliant Lead-free packaging
Product Description
The CM3205 is a dual-output, low noise linear regulator designed to meet SSTL-2 and SSTL-3 specifications for DDR-SDRAM VDDQ supply and termination voltage VTT supply. With integrated power MOSFET's, the CM3205 can source up to 5A of VDDQ current, and source or sink up to 2A VTT current. The typical dropout voltage for VDDQ is 600-mV at 5A load current. The CM3205 provides fast response to transient load changes. Load regulation is excellent, less than 1%, from no load to full load. It also has built-in over-current limits and thermal shutdown at 170C. The CM3205 is packaged in an easy-to-use 5-pin D2PAK (TO263-5) and DPAK (TO252-5). Low thermal resistance (48C/W) allows it to withstand 1.7W (1) dissipation at 85C ambient. It can operate over the industrial ambient temperature range of -40C to 85C.
Applications
* * * * * * * * DDR memory and active termination buses Desktop Computers, Servers Residential and Enterprise Gateways DSL Modems Routers and Switchers DVD recorders 3D AGP cards LCD TV and STB
Typical Application
2.50V , 5A
VDDQ VDDQ
CM3205
ADJSD VDDQ GND VTT VIN
C hip S et
DL0 RT0 DLn RTn
3.3V
1
2
3
4
5
REF Memory 680u 4.7u 887 S/D 845 4.7u 4.7u 680u VREF
DDR
1.25V , 2.5A
680u 1k 1u
(c) 2006 California Micro Devices Corp. All rights reserved. 05/08/06
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1
PRELIMINARY CM3205
Package Pinout
PACKAGE / PINOUT DIAGRAM
Top View
ADJSD
1 2 3 4 5
Top View
ADJSD
1 2 3 4 5
VDDQ
GND VIN VTT
VDDQ
GND VIN VTT
5-Lead TO-263-5 Package CM3205-00TN
Note: This drawing is not to scale.
5-Lead TO-252-5 Package CM3205-00TP
Ordering Information
PART NUMBERING INFORMATION
Lead-free Finish Pins 5 5 Package TO-263-5 TO-252-5 Ordering Part Number1 CM3205-00TN CM3205-00TP Part Marking
Note 1: Parts are shipped in Tape & Reel form unless otherwise specified.
Specifications
ABSOLUTE MAXIMUM RATINGS
PARAMETER VIN to GND Pin Voltages VDDQ ,VTT to GND ADJSD to GND Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering, 10s) RATING [GND - 0.3] to +6.0 [GND - 0.3] to +6.0 [GND - 0.3] to +6.0 -65 to +150 -40 to +85 300 UNITS V V V C C C
(c) 2006 California Micro Devices Corp. All rights reserved.
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PRELIMINARY CM3205
Specifications (cont'd)
ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1)
VIN = 3.3V, typical values are at TA = 25C (unless otherwise specified) SYMBOL VIN VIN VUVLO IQ Supply Voltage Range Under-voltage Lockout UVLO Hysterisis Quiescent Current All outputs are no load 3.15 2.4 3.30 2.7 100 3 5 6.0 1.203 VADJSD = VREF IO = 10 mA to 5A VIN = 3.15V to 3.5V, IO = 10 mA VIN = 3.15V, IO = 5A VOUT = 1.25V VOUT = 1.25V IO = 0A to 2A IO = 0A to -2A Over Temperature Protection Thermal Shutdown Temperature Thermal Shutdown Hysteresis 2 2 8.0 1.215 30 1 0.5 600 2.5 2.5 1 1 170 50 1.227 200 3.50 2.9 V V mV mA mA A V nA % % mV A A % % C C PARAMETER CONDITIONS MIN TYP MAX UNIT S
VDDQ = 0V, VTT = 0V,
ADJSD = 3.3V (shutdown)
VDDQ = 2.5V, VTT = 1.25V, (no load)
VDDQ Regulator Output Current Limit VREF IBIAS VR LOAD VR LINE VDROPOUT VTT Regulator Output Current Limit (Source) Output Current Limit (Sink) VR VTTLOAD Load Regulation Reference Voltage Input Bias Current (IADJ) Load Regulation Line Regulation Dropout Voltage VOUT = 2.5V
(c) 2006 California Micro Devices Corp. All rights reserved. 05/08/06
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
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Tel: 408.263.3214
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PRELIMINARY CM3205
Typical Operating Curves
VTT vs. VDDQ
1.65 1.55 1.45 2.505 1.35 1.25 1.15 1.05 0.95 0.85 0.75 1.5 1.75 2 2.25 2.5 2.75 3 3.25 2.49 -40 -20 0 20 40 60 80 100 120 140
o
VDDQ vs. Temperature
2.51
VDDQ (V)
VTT (V)
2.5 2.495
VDDQ (V)
Temperature C
VDDQ vs. Load Current
3 2.5 600
VDDQ Dropout vs. IDDQ
Dropout Voltage (mV)
500 400 300 200 100 0
VDDQ (V)
2 1.5 1 0.5 0 0 2 4 6 8 10
Ta=25 oC Vin=3.3V
Ta = 25 oC VDDQ=2.5V
0 1 2 3 4 5
IDDQ (A)
IDDQ (A)
VTT vs. Load Current
2.5
Startup into Full Load
Vin
2.0
UVLO
VTT (V)
1.5 1.0 0.5 0.0 -4 -2 0 2 4
VDDQ
Sink
Source
VTT 1V/div 1ms/div
ITT (A)
(c) 2006 California Micro Devices Corp. All rights reserved.
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05/08/06
PRELIMINARY CM3205
Typical Operating Characteristics
VDDQ Transient Response VTT Transient Response
VDDQ VTT
IOUT VIN = 3.3V IOUT Step: 10mA ~ 3A
IOUT VIN = 3.3V IOUT Step: -2.5A ~ +2.5A
Pin Descriptions
PIN DESCRIPTIONS
PIN(S) NAME DESCRIPTION
This pin is for VDDQ output voltage adjustment. The VDDQ output voltage is set using an external resistor divider connected to ADJSD. The output voltage is determined by the following formula:
R1 + R2 V DDQ = 1.215V x -------------------R1
1
ADJSD
where R1 is the ground-side resistor and R2 is the upper resistor of the divider. Connect these resistors to the VDDQ output at the point of regulation. In addition, this input functions as a shutdown pin. Apply a voltage higher than VIN-1.2V to this pin to simultaneously shutdown both VDDQ and VTT outputs. The outputs are restored when the voltage on this pin falls below VIN-1.2V. A low-leakage diode in series with the shutdown input signal is recommended to avoid interference with the voltage adjustment setting.
2 3 4 5
VDDQ GND VIN VTT
VDDQ regulator output voltage pin. GROUND reference pin. The back tab is also ground and serves as the package heatsink. It should be soldered to the circuit board copper to remove excess heat from the IC. Input voltage pin, typically 3.3V from the power supply. VTT regulator output voltage pin, which is preset to 50% of VDDQ.
(c) 2006 California Micro Devices Corp. All rights reserved. 05/08/06
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
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Tel: 408.263.3214
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Fax: 408.263.7846
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PRELIMINARY CM3205
Functional Block Diagram
3.3V S hut Down 2.50V, 5A
1.22V
VDDQ/2, 2.5A
CM3205
Application Information
Powering DDR Memory Double-Data-Rate (DDR) memory has provided a huge step in performance for personal computers, servers and graphic systems. As is apparent in its name, DDR operates at double the data rate of earlier RAM, with two memory accesses per cycle versus one. DDR SDRAM's transmit data at both the rising falling edges of the memory bus clock. DDR's use of Stub Series Terminated Logic (SSTL) topology improves noise immunity and power-supply rejection, while reducing power dissipation. To achieve this performance improvement, DDR requires more complex power management architecture than previous RAM technology. Unlike the conventional DRAM technology, DDR SDRAM uses differential inputs and a reference voltage for all interface signals. This increases the data bus bandwidth, and lowers the system power consumption. Power consumption is reduced by lower operating voltage, a lower signal voltage swing associated with Stub Series Terminated Logic (SSTL_2) and by the use of a termination voltage, VTT. SSTL_2 is an industry standard, defined in JEDEC document
(c) 2006 California Micro Devices Corp. All rights reserved.
JESD8-9. SSTL_2 maintains high-speed data bus signal integrity by reducing transmission reflections. JEDEC further defines the DDR SDRAM specification in JESD79C. DDR memory requires three tightly regulated voltages: VDDQ, VTT, and VREF (see Figure 1). In a typical SSTL_2 receiver, the higher current VDDQ supply voltage is normally 2.5V with a tolerance of 200-mV. The active bus termination voltage, VTT, is half of VDDQ. VREF is a reference voltage that tracks half of VDDQ, 1%, and is compared with the VTT terminated signal at the receiver. VTT must be within 40-mV of VREF.
VDDQ VTT (=VDDQ/2)
Rt = 25 Rs = 25
VDDQ
Line Receiver VREF (=VDDQ/2)
Transmitter
Figure 1. Typical DDR terminations, Class II
6
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PRELIMINARY CM3205
Application Information (cont'd)
The VTT power requirement is proportional to the number of data lines and the resistance of the termination resistor, but does not vary with memory size. In a typical DDR data bus system each data line termination may momentarily consume 16.2-mA to achieve the 405-mV minimum over VTT needed at the receiver:
405mVI terminaton = --------------------- = 16.2mA Rt ( 25 )
the increased package power dissipation and proportionally increased heat generation. VREF is typically routed to inputs with high impedance, such as a comparator, with little current draw. An adequate VREF can be created with a simple voltage divider of precision, matched resistors from VDDQ to ground. A small ceramic bypass capacitor can also be added for improved noise performance.
A typical 128 Mbyte SSTL-2 memory system, with 192 terminated lines, has a worst-case maximum VTT supply current up to 3.11A. However, a DDR memory system is dynamic, and the theoretical peak currents only occur for short durations, if they ever occur at all. These high current peaks can be handled by the VTT external capacitor. In a real memory system, the continuous average VTT current level in normal operation is less than 200 mA. The VDDQ power supply, in addition to supplying current to the memory banks, could also supply current to controllers and other circuitry. The current level typically stays within a range of 2.0A to 3.0A, with peaks up to 4.0A or more, depending on memory size and the computing operations being performed. The tight tracking requirements and the need for VTT to sink, as well as source, current provide unique challenges for powering DDR SDRAM. CM3205 Regulator The CM3205 dual output linear regulator provides all of the power requirements of DDR memory by combining two linear regulators into a single TO-263 or TO-252 5lead package. The VDDQ regulator can supply up to 5A continuous current, and the two-quadrant VTT termination regulator has current sink and source capability to 2A. The VDDQ linear regulator uses a PMOS pass element for a very low dropout voltage, typically 600mV at a 5A output. The output voltage of the VDDQ regulator can be set by an external voltage divider. The second output, VTT, is regulated at VDDQ/2 by an internal resistor divider. The VTT regulator can source, as well as sink, up to 2A continuous current. The CM3205 is designed for optimal operation from a nominal 3.3VDC bus, but can work with VIN as high as 5V. When operating at higher VIN voltages, attention must be given to
(c) 2006 California Micro Devices Corp. All rights reserved. 05/08/06
Input and Output Capacitors The CM3205 requires that at least a 680F electrolytic capacitor be located near the VIN pin for stability and to maintain the input bus voltage during load transients. An additional 4.7F ceramic capacitor between the VIN (pin 4) and the GND (pin 5), located as close as possible to those pins, is recommended to ensure stability. A minimum of a 680F electrolytic capacitor is recommended for the VDDQ output. An additional 4.7F ceramic capacitor between the VDDQ (pin 2) and GND, located very close to those pins, is recommended. A minimum of a 680F, electrolytic capacitor is recommended for the VTT output. This capacitor should have low ESR to achieve best output transient response. SP or OSCON capacitors provide low ESR at high frequency, and thus are a good choice. In addition, place a 4.7F ceramic capacitor between the VTT pin (pin 5) and GND, located very close to those pins. The total ESR must be low enough to keep the transient within the VTT window of 40-mV during the transition for source to sink. An average current step of 0.5A requires:
40mV ESR < -------------- = 40m 1A
Both outputs will remain stable and in regulation even during light or no load conditions. Adjusting VDDQ Output Voltage The CM3205 internal bandgap reference is set at 1.215V. The VDDQ voltage is adjustable by using a resistor divider, R1 and R2:
R2 V OUT = V ADJ x 1 + ------ R1
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PRELIMINARY CM3205
Application Information (cont'd)
where VADJ = 1.215V (-1%). For best regulator stability, we recommend that R1 and R2 not exceed 10-k each. Shutdown Pin 1 (ADJSD) also serves as a shutdown pin. When pin 1 is pulled high, > (VIN - 1.2V), the VDDQ output is turned off and both source and sink MOSFET's of the VTT regulator are set to a high impedance state. During shutdown, the quiescent current is reduced to less than 3mA, independent of output load. It is recommended that a 1N914 or equivalent low leakage diode be placed between Pin 1 and an external shutdown signal to prevent interference with the ADJ pin's normal operation. When the diode anode is pulled low, or left open, the CM3205 is again enabled. Current Limit, Foldback and Over-temperature Protection The CM3205 features internal current limiting with thermal protection. During normal operation, VDDQ limits the output current to approximately 8A and VTT limits the output current to approximately 2A. When VTT is current limiting into a hard short circuit, the output current folds back to a lower level, about 1.5A, until the over-current condition ends. While current limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of
(TOP VIEW)
the package. If the junction temperature of the device exceeds 170-C (typical), the thermal protection circuitry triggers and shuts down both outputs. Once the junction temperature has cooled to below about 120-C, the CM3205 returns to normal operation. Thermal Considerations Both the TO-252 and the TO-263 packages provide a very effective thermal conduction path from the silicon junction into the PC board to which it is mounted. See Figure 2 below. These surface mount packages have a large metal tab that solders to the PC board, where the ground plane can serve as heatsink. This metal tab connects internally to GND (pin 3). A top-layer ground plane is the best in terms of convection air-cooling, a bottom-layer ground plane is less effective, and a middle layer ground plane of a multiple-layer PC board is the least effective. We recommend the metal tab of CM3205 be soldered to a minimum of 3 square inches of ground plane on the top side of the PC board. Use 20 or more platethrough vias to connect the top layer ground plane to ground planes on other layers. When measured in accordance to JEDEC JESD51-3, under natural convection without forced airflow, the Theta junction-to-air (ja) resistance is approximately 48-C/watt for the CM3205-00TN (TO-263-5), and 55-C/watt for the CM3205-00TP (TO-252-5).
(SIDE VIEW)
Vias (0.3mm Diameter)
Top Ground Plane
Via Via (0.3mm Diameter)
Ground Plane Bottom Ground Plane
Power Trace
Figure 2. Thermal Layout
(c) 2006 California Micro Devices Corp. All rights reserved.
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Tel: 408.263.3214
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Fax: 408.263.7846
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www.cmd.com
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PRELIMINARY CM3205
Mechanical Details
TO-263-5 Mechanical Specifications Dimensions for CM3205-00TN devices packaged in 5lead, standard TO-263 packages are presented below. Mechanical Package Diagrams
E S
PACKAGE DIMENSIONS
Package Pins Dimensions A b c D E e L L1 L2 M P S # per tape and reel Millimeters Min 4.34 0.74 0.33 8.92 10.16 14.61 2.29 1.14 0.23 1.14 1.40 Max 4.60 0.89 0.43 9.17 10.67 15.88 2.79 1.40 0.30 1.40 1.91 Min 0.171 0.029 0.013 0.351 0.400 0.575 0.090 0.045 0.009 0.045 0.055
L2 18-22
TO-263
5 Inches Max 0.181 0.035 0.017
e b
1 2
TOP VIEW
Pin 1 Marking
3 4 5
D L
0.361 0.420
7 A P
1.70 REF
0.067 REF 0.625 0.110 0.055 0.012 0.055 0.075
SIDE VIEW 3
7
750 pieces Controlling dimension: inches
c
* This is an approximate amount which may vary.
LEADFORM
0-8
M L1
SEATING PLANE
Package Dimensions for Standard TO-263
(c) 2006 California Micro Devices Corp. All rights reserved. 05/08/06
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PRELIMINARY CM3205
Mechanical Details (cont'd)
TO-252-5 Mechanical Specifications Dimensions for CM3205-00TP devices packaged in 5pin TO-252 packages are presented below. Mechanical Package Diagrams
A
PACKAGE DIMENSIONS
Package Pins Dimensions A B C D G H J K L M P S # per tape and reel Millimeters Min 6.40 5.20 6.80 2.20 0.40 2.20 0.45 0 0.90 5.40 0.50 Max 6.80 5.50 7.20 2.80 0.60 2.40 0.55 0.15 1.50 5.80 0.80 Min 0.252 0.205 0.268 0.087 0.016 0.087 0.018 0 0.035 0.213 0.020
L2
TO-252
5 Inches Max 0.268 0.217 0.283 0.110 0.024 0.094 0.022 0.006 0.059 0.228 0.031 BACK VIEW
D1 B E1 S P G D
FRONT VIEW
1 2
Pin 1 Marking
3 4 5
M
C
1.27 REF 750 pieces
0.05 REF
Controlling dimension: inches SIDE VIEW
H 0-15 J
LEADFORM
0-10
K L
SEATING PLANE
c
Package Dimensions for TO252-5
(c) 2006 California Micro Devices Corp. All rights reserved. 05/08/06
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Tel: 408.263.3214
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Fax: 408.263.7846
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